Converter and a method for controlling a converter

ABSTRACT

In a method for control of a converter for conversion of dc voltage into ac voltage or dc voltage and vice versa, in which an output of the converter may alternatively be connected to a positive pole, a negative pole or a center of a dc voltage side of the converter in the form of different so-called main states, there is carried out, when changing between main states via a so-called minor commutation loop, an extra sequence in the form of a delayed turn-on of semiconductor elements in one unit of the converter relative to semiconductor elements in another unit in a pair of units of the converter.

FIELD OF THE INVENTION AND BACKGROUND ART

The present invention relates to a method for controlling a converteraccording to the preamble to the accompanying claim 1 and to a converteraccording to the preamble to the accompanying independent converterclaim.

The invention thus relates to conversion of voltage in which at leastone side of the converter carries a dc voltage, but the other side doesnot necessarily have to carry an ac voltage, but said output may alsobelong to a second side of a converter in the form of a dc/dc converterused for changing the level of a dc voltage. However, for the purpose ofelucidating the invention, but consequently not limiting the same, thecase of a converter with said output connected to an ac voltage line,that is, conversion between dc voltage and ac voltage, will henceforthbe described. To this end, the case of a converter of VSC (VoltageSource Converter) type intended to generate a train of pulses, byswitching between said main states, with a definite amplitude accordingto a pulse-width modulation pattern on the output of the converter willbe described. Such a converter may be used in all situations where dcvoltage is to be converted into ac voltage and vice versa, wherebyexamples of such uses are in stations of high-voltage direct current(HVDC) installations, in which the dc voltage is normally converted intothree-phase ac voltage or vice versa, or in so-called back-to-backstations where ac voltage is first converted into dc voltage and this dcvoltage then converted into ac voltage, as well as in SVCs (Static VarCompensators), where the dc-voltage side consists of one or more freelyhanging capacitors. The ac side of the converter could also be connectedto an ac motor for driving it, or to an ac generator.

Further, it is pointed out that the method is directed to control of asaid converter that exhibits at least said six units, which means thatat least three different levels may be obtained for the voltage on saidoutput, but it is fully possible for the converter to exhibit severalsuch units, so that more than four main states and also more than threelevels of the voltage on the output may be achieved. In this context,several converters of this kind may form part of a converter for severalphases, such as for three phases, but it may also be designed to form onits own a converter for conversion between dc voltage a single-phase acvoltage.

Further, the invention is not limited to any special voltage levels ofsaid first dc voltage side or magnitude of power that is to be handled.The former is advantageously within the interval of 1 kV to 500 kV.

One advantage of using a converter with at least three levels instead ofa two-level bridge when converting ac voltage to dc voltage is thatconsiderably lower frequencies for switching the semiconductor elementsof the units according to the pulse-width modulation pattern may be usedfor achieving a curve shape of the ac voltage side of a given quality.In this way, the switching losses may be considerably reduced so that itis also possible to transmit higher powers through such a three-levelconverter than through a two-level bridge, since higher on-state lossesmay be allowed. At the same time, harmonics generated by the pulse-widthmodulation process are reduced.

One method of the kind defined in the introductory part of thedescription is previously known from applicant's own Swedish patent 517427. This Swedish patent describes a method that constitutes animprovement of prior art such methods for control of a converter withsaid six units by proposing how the switching losses are to bedistributed more uniformly than previously between the different units.By utilizing, in an embodiment of the method according to Swedish patent517 427, only four different states of the semiconductor elements of theunits, the actual method for controlling the semiconductor elements willbe very simple. It is pointed out that, in practice, there is, ofcourse, a fifth possible state of this embodiment, namely when theconverter is out of operation and when all the semiconductor elementsare turned off. Since the semiconductor elements of the first and sixthunits are controlled to assume the same position, turned on or off, inthe respective main state, and since the semiconductor elements in thefourth and fifth units are controlled to assume the same position,turned on or off, in the respective main state, it is possible to usethe same control signal for the semiconductor elements in the first andsixth units and in the fourth and fifth units, respectively.

Although it is advantageous to interlock, so to speak, the semiconductorelements in four of the units pair by pair in this way, the inventors ofthe present invention have realized that there may sometimes ariseproblems in giving the semiconductor elements of such a pair of unitscontrol signals for turning them on or off simultaneously. This is dueto the fact that the semiconductor element will react differently tosuch a control signal in dependence on whether the semiconductor elementis current-carrying during the switching or not, that is to say, whetherit is a question of a passive voltage switching or an actual currentcommutation. A passive voltage switching may proceed considerably fasterthan an actual current commutation, so that in one case thesemiconductor element is turned on or off significantly more rapidlythan in the other case. Considering the condition of current directionduring commutation, this may imply that brief high voltage peaks couldbe achieved across any said unit, which could destroy the semiconductorelement in question. Alternatively, the semiconductor elements, or atleast such elements in certain units, must be designed in most cases tobe oversized as regards voltage withstand capability in order to managesuch voltage peaks, which makes them unnecessarily expensive.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a method as well as aconverter of the kind defined in the introduction, which make itpossible to overcome the above-mentioned drawbacks, hence making itpossible to ensure that no semiconductor element is destroyed during theswitching operations because of voltage peaks without this requiring anyoversizing of the semiconductor elements.

This object is achieved according to the invention by the provision of amethod of the kind defined in the introduction, in which, when changingbetween main states via a so-called commutation loop, that is, changingbetween a connection of the positive pole to the output and the zerostate according to the third main state, or changing between aconnection of the negative pole to the output and the zero stateaccording to the fourth main state, at least when the current directionwould entail a voltage peak on essentially the entire voltage betweensaid positive pole and said negative pole across that of the second orthe third unit which does not belong to the commutation loop in thosecases where the semiconductor elements which are to be turned on in thecoming main state and belong to a said pair of units were to be turnedon simultaneously, an extra sequence is carried out in the form of adelayed turn-on of the semiconductor element in one unit of the latterpair relative to the semiconductor element in the other unit of saidpair.

Thus, the inventors have realized that said problem with voltage peaksarises when changing between main states via a so-called commutationloop, and that this problem may be solved by the introduction of a delayof the turn-on of the semiconductor element in one unit of a said pairof units relative to the semiconductor element in the other unit of saidpair during such commutation. By such a delay, it will be ensured thatnever essentially more than half the voltage between said positive poleand said negative pole will be applied across the second or third unit.Thus, the semiconductor elements of said units need not be oversized asfar as voltage withstand capability relative to the semiconductorelements of other units of the converter is concerned.

According to a preferred embodiment of the invention, said extrasequence is always carried out when changing main states according to asaid small commutation loop independently of the current direction atthe output. It has been found that the problem of said voltage peaks isdue to the current direction during a said commutation, but by makingthe carrying out of the extra sequence independent of the currentdirection, the method according to the invention may be simplifiedconsiderably and its reliability be increased.

In this connection it has been found that it is advantageous to turn onthe semiconductor element in the outer unit, that is, the first orfourth unit, of the respective pair of units with a delay relative tothe other unit, that is, the sixth or fifth one, in the pair.

According to another preferred embodiment of the invention, said delayis smaller than one-tenth, preferably smaller than one-hundredth, of thenormal duration of a said main state. Thus, the point is that theintermediate state that is achieved by said delay is to have a duration,relative to the main states, which in this context is exceedingly shortand therefore, in practice, does not influence the result of theoperation of the converter otherwise than by avoiding voltage peaksacross the semiconductor elements in question.

According to another preferred embodiment of the invention, thesemiconductor elements of the units are controlled such that, betweentwo main states, a so-called blanking state is always achieved to avoidthat semiconductor elements which are not allowed to be turned onsimultaneously should be briefly turned on, at least partly, and thatduring this state such a semiconductor element can be turned off beforeanother element is thereafter turned on. In this way, partial shortcircuits of the converter in question can be avoided, for example shortcircuits of capacitors used on the dc-voltage side of the converter todefine the dc voltage.

According to a further preferred embodiment of the invention, thesemiconductor elements are controlled to minimize the duration of stateslying between said main states, with the semiconductor elements in thesecond and sixth units simultaneously being turned on or those in thethird and fifth units being simultaneously turned on to avoid parallelcurrents in the converter. The reason is that it has been found thatparallel currents associated with undefined operating states of theconverter in dependence on the current direction at the output of theconverter may be achieved if the semiconductor elements in the secondand sixth units or those in the third and fifth units are turned onsimultaneously in intermediate states lying between the main states. Theproblem with such parallel currents and undefined operating states ofthe converter is solved by making these intermediate states as short asis at all possible.

According to still another preferred embodiment, when changing betweenmain states via a large commutation loop, that is, when changing betweenthe first main state and the fourth main state or changing between thesecond main state and the third main state, the semiconductor elementsbelonging to the same pair of units are controlled with one and the samecontrol pulse so that both elements during the change can be held in thesame position, turned off or turned on. It has been found that,independently of the direction of the current at the output of theconverter, no problems with said voltage peaks arise during commutationaccording to the so-called large commutation loop, such that the methodmay be simplified in such a case by using one and the same control pulsefor the semiconductor elements belonging to the same pair.

According to yet another preferred embodiment of the invention, themethod is carried out on a converter with several said semiconductorelements connected in series in each said unit, and the semiconductorelements belonging to the same unit are controlled by one and the samecontrol pulse. The method according to the invention is especially wellsuited for converters in which a series connection of a plurality ofsemiconductor elements is required in order for them to maintain thevoltage that the unit must maintain in its blocking state, since in sucha case certain semiconductor elements may already have a somewhat highervoltage across them than other semiconductor elements because of certainminor differences between the semiconductor elements, and in such a caseit is extremely important that said voltage peaks can be avoided toeliminate the risk of these very semiconductor elements being destroyedand hence also the other semiconductor elements being destroyed.

The invention also relates to a converter according to the accompanyingindependent converter claims, and the advantages of such a converter inrelation to prior art converters of that kind should be completely clearfrom the description above of the method according to the invention andthe preferred embodiments thereof.

The invention also relates to a computer program and to acomputer-readable medium according to the corresponding claims. It isreadily realized that the method according to the invention as definedin the accompanying set of method claims is well suited to be carriedout by program instructions from a processor which is influenced by acomputer program provided with the relevant program steps.

Additional advantages and advantageous features of the invention willbecome clear from the following description and the other dependentclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention, mentioned as examples, will bedescribed below with reference to the accompanying drawings, wherein:

FIG. 1 schematically illustrates a converter of three-level type of thekind to which the method according to the invention may be applied,

FIG. 2 schematically illustrates how a pulse-width modulation pattern isplaced on the phase output of a converter according to FIG. 1, and

FIG. 3 is a simplified block diagram illustrating the principle ofcontrolling a converter according to FIG. 1 according to the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

FIG. 1 illustrates the composition of a three-level converter of thekind described in the above-mentioned Swedish patent 517 427. It isillustrated here how the converter exhibits three so-called phase legs1–3, each having a phase output 4–6 for connection of the ac-voltageside of the converter via a reactor and/or transformer to a three-phaseac-voltage network, but hereinafter only one of these phase legs will bediscussed. It is also fully possible for the converter to be connectedto a single-phase ac-voltage network or the ac-voltage side may beconnected, besides to the ac network, to a generator or a motor. Theconverter is a so-called VSC converter that exhibits a series connectionof four units S1–S4, arranged between two poles, one positive 7 and onenegative 8, of a dc-voltage side of the converter, said units eachcomprising a gate turn-off semiconductor element 13–16 and a diode 17–20connected in anti-parallel therewith and being given orders according tothe order in the series connection from the positive to the negativepole.

Two series-connected capacitors 21, 22 are arranged between said twopoles, and a point 23 (the centre of the dc-voltage side) between these(which is normally the case) is connected to ground 9 via an impedanceZ, whereby this impedance may vary from zero (=direct grounding of thecentre of the dc-voltage side) to a value X (=impedance grounding of thecentre of the dc-voltage side, via e.g. a resistance R or an inductanceL) up to a value X_(max) (=non-grounded centre, where the grounding isonly determined by stray capacitances between the centre of thedc-voltage side and ground), so that in this way the potentials +U/2 and−U/2, respectively, are provided at each respective pole, whereby U isthe voltage between the two poles 7, 8.

A second centre 24 of the series connection between the first and secondunits is connected, via a fifth unit S5 with the diode 26 with aconducting direction with respect to the phase output 4 opposite to theconducting direction of the diode of the second unit and a gate turn-offsemiconductor element 10 connected in anti-parallel therewith, to thecentre of the dc-voltage side, and a third centre 27 of the seriesconnection between the third and fourth units is connected, via a sixthsaid unit S6 with the diode 29 with a conducting direction with respectto the phase output opposite to the diode of the third unit and a gateturn-off semiconductor element 11 connected in anti-parallel therewith,to the centre of the dc-voltage side.

The gate turn-off semiconductor elements of the units S1–S6 may, forexample, be IGBTs or GTOs. Although only one IGBT or GTO per unit hasbeen shown, this may represent a plurality of series-connected,simultaneously controlled IGBTs or GTOs, which is also normally thecase, since a relatively large number of such semiconductor elements isrequired to maintain the voltage that each unit has to maintain in theblocked state when, for example, the dc-voltage side has a voltageexceeding 10 kV. Also, each shown diode, so-called freewheeling diode,may represent a large number of series-connected diodes.

The semiconductor elements included in the converter are controlled viaa schematically indicated device 30 to turn on and off to alternatelyconnect the centre, the positive pole and the negative pole of thedc-voltage side to the phase output of the respective phase leg forgenerating a train of pulses with definite amplitudes and according to apulse-width modulation pattern (PWM) on the phase output. In thiscontext, the pulse-width modulation frequency is considerably higher,advantageously at least five times higher, more preferred at least 10times higher and most preferred at least 20 times higher, than thefundamental frequency of the normally essentially sinusoidal alternatingcurrent on the phase output of the converter. Thus, the pulse-widthmodulation frequency may preferably be in the order of magnitude of 1–2Khz, whereas the fundamental frequency, that is, the frequency of thefundamental tone of the phase current on the phase output, is typically50 Hz or 60 Hz. In case of a generator-connected or a motor-connectedconverter, however, the frequency of the current may vary within a largerange.

The converter may be operated in different ways, such as fortransmission of active power as a rectifier or an inverter, or fortransmission of reactive power, or for transmission of a combination ofactive and reactive power.

The centre 23 of the dc-voltage side is connectible to the phase output4 by two different so-called zero states, namely, a first one in whichthe second S2 and the fifth S5 unit are in a conducting state, and asecond one, in which the third S3 and the sixth S6 unit are in aconducting state. This possibility of choosing zero states isadvantageously utilized for controlling the converter so that the sum ofthe switching and on-state losses is distributed more uniformly betweenthe semiconductor elements of four of the six units, and how such acontrol may take place is described in greater detail in Swedish patent517 427.

The device 30 is advantageously arranged to control the semiconductorelements of the units so that the two zero states are assumedessentially the same number of times per unit of time, and in thiscontext it is advantageous to control the semiconductor elements suchthat essentially each time a said zero state is to be chosen, that zerostate is chosen which is opposite to the zero state which, with respectto time, immediately precedes it.

The control device 30 is designed to control the semiconductor elementsof the units S1–S6 to be turned on and off so that alternately four mainstates are obtained in the converter in the form of a connection of theoutput to the positive pole of the first side according to a first one,in which thus at least the semiconductor elements of S1 and S2 must beturned on, to the negative pole according to second one, in which atleast the semiconductor elements of S3 and S4 must be turned on, or thecentre via any of said two zero states. As in the case of the controlmethod according to Swedish patent 517 427, in the method according tothe invention an interlock is made between the pairs of units S1, S6 andS4, S5 with regard to their position in the respective main state, sothat the elements belonging to the same pairs are simultaneously turnedon or off. In this context, it is ensured that the semiconductorelements of the opposite units have turn-off signals before thesemiconductor element to be turned on has a turn-on signal. If no suchinterlock should be present and, for example, S1, S6 be turned on beforeS4, S5 are turned off when changing from the fourth to the first state,then the capacitors 21 and 22 will be briefly short-circuited and largeshort circuit currents arise.

FIG. 2 illustrates what a pulse-width modulation pattern may typicallylook like for a converter of the kind shown in FIG. 1. Here, the shownsine curve 31 is the voltage reference value of the phase output 4 ofthe converter, whereas it is clear that when said reference value ispositive, the positive pole and the centre 23 of the dc-voltage side arealternately connected to the phase output, that is, positive pulses andzero pulses while a shifting width is being changed, whereas when saidreference value is negative, a change between negative pulses and zeropulses is made.

FIG. 3 illustrates very schematically how the control by means of thecontrol device 30 is carried out in practice. A reference valuecorresponding to the voltage reference value of the phase output arrivesat 33 at a pulse-width modulation generator 34, which prepares thepulse-width modulation pattern shown in FIG. 2 and sends a pulse-widthmodulation signal on its output 35, which orders a positive, a negativeor a zero pulse on the phase output, to a zero-stage selector 36, whichsends a pulse-width modulation signal containing information on whichzero state to be chosen when a zero pulse is to be placed on the phaseoutput, to a means 37 for controlling the semiconductor elements of thedifferent units S1–S6 to be turned on or off, which is illustrates bythe six arrows 38 to the semiconductor elements.

The inventors of the present invention have realized that at certaincommutations between different main states in a method according toSwedish patent 517 427, brief voltage peaks on essentially the wholevoltage U between the two poles of the dc-voltage side will be appliedacross any of the two inner units, that is, S2 or S3. This results in aconsiderable risk of failure of one or several semiconductor elements insuch a unit, unless the units are greatly over-sized as far as voltagewithstand capability is concerned, which is costly. More particularly,this problem arises when changing between main states via a so-calledsmall commutation loop, that is, between the connection of the positivepole to the output and the third zero state or the connection of thenegative pole to the output and the fourth zero state. This is due tothe units behaving differently depending on whether it is a question ofa passive voltage switching of the semiconductor elements or whether itis a question of an actual current commutation. This can be exemplifiedby changing between the first main state, in which S1, S2 and S6 areturned on, and the third main state, in which S2, S5 and S4 are turnedon. If in such a case, after turning off S1 and S6, S4 and S5 were to beturned on simultaneously, then, because S1 has carried current, it wouldtake quite a substantial amount of time to turn on the semi-conductorelement in S5 and commutate the current over from S1 to that element, sothat briefly the output 4 would still have the same potential as thepositive pole of the dc-voltage side. If, on the other hand, thesemiconductor element in S4 were to turn on simultaneously, which wouldinvolve a passive voltage switching without any current commutation,then the potential of the negative pole would be connected considerablyfaster to point 27 between S3 and S4, so that the whole voltage betweenthe two dc-voltage poles would briefly lie across S3. However, theinvention solves this problem by the introduction, when changing betweenmain states via a small commutation loop, of an extra sequence in theform of a delayed turn-on of the semiconductor element in one unit ofthat pair which is to be turned on relative to the semiconductor elementin the other unit of said pair. In the example just described, thisimplies that the semiconductor element in S4 is turned on with a delayrelative to the semiconductor element in S5, so that said currentcommutation has had time to occur and the phase output 4 is at zeropotential before the semiconductor element in S4 is turned on, and henceonly half the dc voltage will be applied across S3. This delay is thenvery short in relation to the normal duration of a said main state, andthe ratio is typically such that the delay is smaller than one-tenth,preferably smaller than one-hundredth, of the normal duration of a saidmain state, and may, for example, be 5 μs/1000 μs.

In addition to these so-called extra sequences during a so-called smallcommutation loop, the semiconductor elements of the units are controlledsuch that, between two main states, there is always a so-called blankingstate to avoid that semiconductor elements which are not allowed to beturned on simultaneously should briefly be so, at least partly, and thatduring this state such a semiconductor element has time to turn offbefore another such element is thereafter turned on. Such blankingstates have a duration of approximately the same order of magnitude assaid delay and are thus exceedingly short in relation to the normalduration of a main state. They are introduced between all main states,also during so-called large commutation loops when a said extra sequenceis not carried out.

In addition, the semiconductor elements are controlled to minimize theduration of states, lying between said main states, with thesemiconductor elements in the second and sixth units beingsimultaneously turned on or those in the third and fifth units beingsimultaneously turned on to avoid parallel currents in the converter.

This leads to the following control schemes for changing between mainstates via a so-called commutation loop according to the presentinvention:

Tables 1–4 show the methods according to the invention with extrasequences during a change between main states via a so-called smallcommutation loop, wherein B indicates a blanking state and E an extrasequence. In a corresponding manner, changing between main states viathe two so-called commutations loops is summarized in table 5 and table6. There, it is clear that no extra sequences are used.

TABLE 1 S1 S2 S3 S4 S5 S6 1+ 1 1 0 0 0 1 B 0 1 0 0 0 0 E 0 1 0 0 1 0 3N0 1 0 1 1 0

TABLE 2 S1 S2 S3 S4 S5 S6 3N 0 1 0 1 1 0 E 0 1 0 0 1 0 E 0 1 0 0 1 1 B 01 0 0 0 1 1+ 1 1 0 0 0 1

TABLE 3 S1 S2 S3 S4 S5 S6 2− 0 0 1 1 1 0 B 0 0 1 0 0 0 E 0 0 1 0 0 1 4N1 0 1 0 0 1

TABLE 4 S1 S2 S3 S4 S5 S6 4N 1 0 1 0 0 1 E 0 0 1 0 0 1 E 0 0 1 0 1 1 B 00 1 0 1 0 2− 0 0 1 1 1 0

TABLE 5 S1 S2 S3 S4 S5 S6 1+ 1 1 0 0 0 1 B 1 0 0 0 0 1 4N 1 0 1 0 0 1 B1 0 0 0 0 1 1+ 1 1 0 0 0 1

TABLE 6 S1 S2 S3 S4 S5 S6 2− 0 0 1 1 1 0 B 0 0 0 1 1 0 3N 0 1 0 1 1 0 B0 0 0 1 1 0 2− 0 0 1 1 1 0

The change according to table 1 has already been commutated higher up.The change according to table 2 may be explained as follows. Theintermediate state with S2 and S5 being conducting is introduced beforethe second intermediate state with S2, S5 and S6 being conducting, sinceotherwise there is a risk of S4 and S6 being briefly simultaneouslyturned on and short-circuiting the capacitor 22. The extra sequence inthe form of the state with S2, S5 and S6 being turned on is there toforce the centre 27 between S3 and S4 to become zero before the phaseoutput is connected to the positive pole. The blanking state with S2 andS6 being turned on is important since otherwise it would have beennecessary to turn off S5 simultaneously with turning on S1, and for thereason stated above it is not desired to control the semiconductorelements in two units in a small commutation loop simultaneously.

Tables 3 and 4 need no further explanation, since the same problemsarise there as when changing according to table 1 and table 2 and thesechanges are mirror-symmetrical relative to the output 4 and the centre23 relative to the former

As already mentioned above, the states with S3 S5 S6, S3 S5, S2 S5 S6 orS2 S6 being simultaneously conducting are to be minimized to limit theduration of parallel currents in the circuit as far as possible.

To simplify the control method according to the invention, this is notdone depending on the direction of the current at the output 4, althoughcertain problems that are solved by said extra sequences only occur at agiven current direction and, at an opposite current direction, the extrasequence thus could be omitted. However, this would lead to aconsiderably more complicated control method.

The invention is not, of course, in any way limited to the preferredembodiments described above, but a number of possibilities ofmodifications thereof should be obvious to a person skilled in the artwithout this person deviating from the fundamental concept of theinvention as defined in the claims.

A number of other possibilities of control schemes utilizing thefundamental concept of the invention should be obvious. to personsskilled in the art.

For example, it is fully possible to sense the direction of the currentat the output and to make the performance of an extra sequence or notdependent on the current direction. It is also possible for theconverter in question to exhibit additional said units to providepossibilities for more than three levels on the output.

1. A method for control of a converter for conversion of dc voltage intoac voltage or dc voltage and vice versa, comprising a series connectionof four units, arranged between two poles, one positive pole and onenegative pole, of a first side in the form of a dc-voltage side of theconverter, each of said units comprising a gate turn-off semiconductorelement and a diode connected in antiparallel therewith and being givenorders according to the order in the series connection from the positiveto the negative pole, a line on the second side of the converter beingconnected to a first center, designated output, of the series connectionbetween the second and third units, means arranged to provide, on saidfirst side, a center between the two poles and to place these poles atthe same voltage but with opposite signs in relation to the center ofthe first side, wherein a second center of the series connection betweenthe first and second units is connected, via a fifth said unit with agate turn-off semiconductor element and with the diode connected inantiparallel therewith with the conducting direction with respect to theoutput opposite to the conducting direction of the diode of the secondunit, to the center of the first side, and a third center of the seriesconnection between the third and fourth units is connected, via a sixthsaid unit with a gate turn-off semiconductor element and with the diodeconnected in antiparallel therewith with a conducting direction withrespect to the output opposite to the diode of the third unit, to thecenter of the first side, wherein the semiconductor elements of theunits are controlled to be turned on and off such that alternately fourmain states are obtained in the converter in the form of a connection ofthe output to the positive pole of the first side according to a first,to the negative pole according to a second, or the center via any of twodifferent so-called zero states, namely, a third, in which the secondand fifth units are in a conducting state, and a fourth, in which thethird and sixth units are in a conducting state, wherein the first andsixth units form a pair in that said semiconductor elements arecontrolled to assume, in the respective main state, the same position,turned on or off, and the fourth and fifth units form a pair in thatthese semiconductor elements are controlled to assume, in the respectivemain state, the same position, turned on or off, and wherein a changebetween the first and second main states is always made via the third orfourth zero state, wherein when changing between main states via aso-called small commutation loop, that is, changing between a connectionof the positive pole to the output and the zero state according to thethird main state, or changing between a connection of the negative poleto the output and the zero state according to the fourth main state, atleast when the current direction would entail a voltage peak onessentially the entire voltage between said positive pole and saidnegative pole across that of the second or the third unit which does notbelong to the commutation loop in those cases where the semiconductorelements which are to be turned on in the coming, main state and belongto a said pair of units were to be turned on simultaneously, an extrasequence is carried out in the form of a delayed turn-on of thesemiconductor element in one unit of the latter pair relative to thesemiconductor element in the other unit of said pair.
 2. The methodaccording to claim 1, wherein said extra sequence is always carried outwhen changing main states according to a said small commutation loopindependently of the current direction at the output.
 3. The methodaccording to claim 1, wherein it is the semiconductor element in theouter unit, that is, the first or fourth unit, of the respective pair ofunits that is turned on with a delay relative to the other unit, thatis, the sixth or fifth, in the pair.
 4. The method according to claim 1,wherein when changing from the first to the third main state, thesemiconductor element in the fourth unit is turned on with a delayrelative to the semiconductor element in the fifth unit.
 5. The methodaccording to claim 1, wherein when changing from the second to thefourth main state, the semiconductor element in the first unit is turnedon with a delay relative to the semiconductor element in the sixth unit.6. The method according to claim 1, wherein when changing from the thirdto the first main state, the semiconductor element in the first unit isturned on with a delay relative to the semiconductor element in thesixth unit.
 7. The method according to claim 1, wherein when changingfrom the fourth to the second main state, the semiconductor element inthe fourth unit is turned on with a delay relative to the semiconductorelement in the fifth unit.
 8. The method according to claim 1, whereinsaid delay is smaller than one tenth, preferably smaller thanone-hundredth, of the normal duration of a said main state.
 9. Themethod according to claim 1, wherein the semiconductor elements of theunits are controlled such that, between two main states, a so-calledblanking state is always achieved to avoid that semiconductor elementsthat are not allowed to be turned on simultaneously should briefly beso, at least partly, and that, during this state, such a semiconductorelement has time to turn off before another such element is thereafterturned on.
 10. The method according to claim 9, wherein thesemiconductor elements are controlled to assume said blanking state fora period of time that lasts less than one-tenth, preferably less thanone-hundredth, of the normal duration of a said main state.
 11. Themethod according to claim 1, wherein the first main state is achieved bycontrolling the semiconductor elements in the first, second and sixthunits to be turned on, the second main state by controlling thesemiconductor elements in the third, fourth and fifth units to be turnedon, the third main state by controlling the semiconductor elements inthe second, fourth and fifth units to be turned on, and the fourth mainstate by controlling the semiconductor elements in the first, third andsixth units to be turned on.
 12. The method according to claim 11,wherein when changing from the first main state to the third main state,the semiconductor elements in the first and sixth states are firstturned off, then the semiconductor element in the fifth unit is turnedon, and finally the semiconductor element in the fourth unit is turnedon.
 13. The method according to claim 11, wherein when changing from thethird main state to the first main state, the semiconductor element inthe fourth unit is fist turned off, then the semiconductor element inthe sixth unit unit is turned on, whereupon the semiconductor element inthe fifth unit is turned off, and, finally, the semiconductor element inthe first unit is turned on.
 14. The method according to claim 11,wherein when changing from the second main state to the fourth mainstate, the semiconductor elements in the fourth and fifth units are fistturned off, then the semiconductor element in the sixth unit unit isturned on, and, finally, the semiconductor element in the first unit isturned on.
 15. The method according to claim 11, wherein when changingfrom the fourth main state to the second main state, the semiconductorelement in the first unit is fist turned off, then the semiconductorelement in the fifth unit unit is turned on, whereupon the semiconductorelement in the sixth unit is turned off, and, finally, the semiconductorelement in the fourth unit is turned on.
 16. The method according toclaim 1, wherein the semiconductor elements are controlled to minimizethe duration of states, lying between said main states, with thesemiconductor elements in the second and sixth units beingsimultaneously turned on, or those in the third and fifth units beingsimultaneously turned on to avoid parallel currents in the converter.17. The method according to claim 1, wherein when changing between mainstates via a large commutation loop, that is, when changing between thefirst main state and the fourth main state or when changing between thesecond main state and the third main state, the semiconductor elementsbelonging to the same pair of units are controlled with one and the samecontrol pulse to be both maintained constantly in the same position,turned off or on, during the changing.
 18. The method according to claim1, wherein the semiconductor elements of the units are controlled suchthat the two zero states are assumed essentially the same number oftimes per unit of time.
 19. The method according to claim 18,characterized in that wherein the semiconductor elements of the unitsare controlled such that essentially each time a said zero state is tobe chosen, that zero state is chosen which is opposite to the zero statewhich, with respect to time, immediately precedes it.
 20. The methodaccording to claim 1, wherein it is carried out on a converter withseveral said semiconductor elements connected in series in each saidunit, and that the semiconductor elements belonging to the same unit arecontrolled by one and the same control pulse.
 21. The method accordingto claim 1, wherein it is semiconductor element in the form of InsulatedGate Bipolar Transistors that are controlled to be turned on and off.22. The method according to claim 1, wherein it is carried out on aconverter in the form of a VSC converter for conversion of ac voltageinto dc voltage and vice versa, with said line formed from an ac-voltagephase conductor for generating, by changing between the main states, atrain of pulses with definite amplitudes according to a pulse-widthmodulation pattern on the output of the converter.
 23. The methodaccording to claim 22, wherein it is a VSC converter with a dc-voltageside formed from a dc-voltage network for transmission of high-voltagedirect current and the ac-voltage phase conductor belonging to anac-voltage network that is controlled.
 24. The method according to claim22, wherein it is two VSC converters of a back-to-back station withtheir ac-voltage sides connected to one and the same, or to separate,ac-voltage networks and their dc-voltage sides connected to each otherthat are controlled.
 25. The method according to claim 22, wherein it isa VSC converter included in an Static Var Compensator with thedc-voltage side formed from freely hanging capacitors and the ac-voltagephase conductor belonging to an ac-voltage network that is controlled.26. The method according to claim 1, wherein it is a VSC converter withsaid output connected to an ac motor that is controlled.
 27. The methodaccording to claim 1, wherein it is a VSC converter with said outputconnected to an ac generator that is controlled.
 28. A converter forconversion of dc voltage into ac voltage or dc voltage and vice versa,comprising a series connection of four units, arranged between twopoles, one positive pole and one negative pole, of a first side in theform of a dc-voltage side of the converter, each of said unitscomprising a gate turn-off semiconductor element and a diode connectedin antiparallel therewith and being given orders according to the orderin the series connection from the positive to the negative pole, a lineon the second side of the converter being connected to a first center,designated output, of the series connection between the second and thirdunits, means arranged to provide, on said first side, a center betweenthe two poles and to place these poles at the same voltage but withopposite signs in relation to the center of the first side, wherein asecond center of the series connection between the first and secondunits is connected, via a fifth said unit with a gate turn-offsemiconductor element and with the diode connected in antiparalleltherewith with the conducting direction with respect to the outputopposite to the conducting direction of the diode of the second unit, tothe center of the first side, and a third center of the seriesconnection between the third and fourth units is connected, via a sixthsaid unit with a gate turn-off semiconductor element and with the diodeconnected in antiparallel therewith with a conducting direction withrespect to the output opposite to the diode of the third unit, to thecenter of the first side, wherein the converter also comprises a devicearranged to control the semiconductor elements of the units to be turnedon and off to alternately achieve four main states of the converter inthe form of a connection of the output to the positive pole of the firstside according to a first, to the negative pole according to a second orto the center via any of two different so-called zero states, namely athird, in which the second and fifth units are in a conducting state,and a fourth, in which the third and sixth units are in a conductingstate, wherein the first and sixth units form a pair in that the deviceis arranged to control the semiconductor elements thereof to assume, inthe respective main state, the same position, turned on or off, and thefourth and fifth units form a pair in that the device is arranged tocontrol the semiconductor elements thereof to assume, in the respectivemain state, the same position, turned on or off, and wherein the deviceis arranged to control the semiconductor elements such that a changebetween the first and second main states is always made via the third orfourth zero state, wherein the device is arranged, when changing betweenmain states via a so-called small commutation loop, that is, changingbetween a connection of the positive pole to the output and the zerostate according to the third main state, or a connection of the negativepole to the output and the zero state according to the fourth mainstate, at least when the current direction would entail a voltage peakon essentially the entire voltage between said positive pole and saidnegative pole across that of the second or the third unit which does notbelong to the commutation loop in those cases where the semiconductorelements which are to be turned on in the coming main state and belongto a said pair of units were to be turned on simultaneously, to controlthese semiconductor elements according to an extra sequence in the formof a delayed turn-on of the semiconductor element in one unit of thelatter pair relative to the semiconductor element in the other unit ofsaid pair.
 29. A computer program which is loadable directly into theinternal memory of a computer, said computer program comprising softwarecode portions for controlling the steps of claim 1, when running theprogram on the computer.
 30. The computer program according to claim 29,provided at least partly via a network such as the Internet.
 31. Acomputer-readable medium with a program registered thereon, wherein theprogram is designed to bring a computer to control the steps accordingto claim 1.